FXLS93421 datasheet(114/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.6.2 Inertial sensor self-test interface

The analog self-test interface applies a voltage to the g-cell, causing deflection of the

proof mass. The resulting sensor data can be compared against the values stored in the

Self-test Deflection Registers (See Section 11.2.37). The self-test interface is controlled

through register write operations to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register

described in Section 11.2.27. A diagram of the self-test interface is shown in Figure 19.

aaa-030613

SELFTEST

VOLTAGE

GENERATOR

STV_HIGH

High/Low Self Test Select

STV_LOW

TRANSDUCER

The following signals are all

selected by the ST_CTRL[3:0] bits

- SELFTEST ENABLE

- SELFTEST POLARITY

- High/Low Self Test Select

ENDINIT

SELFTEST ENABLE

SELFTEST POLARITY

SELFTEST ENABLE

SELFTEST POLARITY

Figure 19. Self-test interface

Two self-test voltages are available for each device range. The self-test voltage is

selected via the ST_CTRL[3:0] bits.

Self-test can be verified via the following methods:

11.6.2.1 Raw self-test deflection verification

In DSI3 mode, SPI mode or I2C mode, the raw self-test deflection can be verified against

raw self-test limits in Section 10.7.

11.6.2.2 Delta self-test deflection verification

In DSI3 mode, SPI mode or I2C mode, the raw self-test deflection can be verified against

the nominal temperature self-test deflection value recorded at the time the device was

produced. The production self-test deflection is stored in the CHx-_STy_z register as

defined in Section 11.2.37. The Delta Self-test Deflection limits can then be determined

by Equation 3 and Equation 4:

(3)

Note: This value is truncated.

(4)

Note: This value is rounded up.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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