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FXLS93421 Datasheet(PDF) 115 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 115 Page - NXP Semiconductors |
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115 / 254 page ![]() NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Where: ΔSTACC = The accuracy of the self-test deflection relative to the stored deflection as specified in Section 10.8. STDATA = The value stored in the appropriate CHx_STy_z register as defined in Section 11.2.37. 11.6.2.3 Startup digital self-test In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set), the user can activate a digital self-test by writing to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register. The digital self-test inputs a known signal stream into the front end of the DSP. After a delay defined by the low-pass filter selected, the output sensor data reaches a fixed value which can be verified by the user. The digital self-test values are listed in Section 11.2.27.1. 11.6.2.4 Fixed pattern self-test In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set), the user can activate a fixed pattern self-test by writing to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register. Fixed pattern self-tests force the DSP output to a set of known values, enabling the user to verify each bit of the sensor data. The fixed pattern self-test values are listed in Section 11.2.27.1. 11.6.2.5 PSI5 automatic startup self-test procedure Figure 20 shows the PSI5 self-test procedure which is run automatically at startup on each channel if the device is a PSI5 device. The minimum gain settings are used for this procedure: U_SNS_SHIFT = '00', U_SNS_MULT = 0x00. FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 115 / 254 |
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