FXLS93421 datasheet(118/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Description

Sample Time

(µs)

Data

width

(Bits)

Sign

(Bits)

Over

range

(Bits)

Signal

width

(Bits)

Signal

margin

(Bits)

Typical

block

latency

Reference

F User Scaling

16, 32, 64

N/A

Section 11.6.4.5

H Down Sample

32, 64, 128

N/A

Section 11.6.4.7

J Secondary Down Sample

256

N/A

Section 11.6.4.6

K Offset low-pass filter

256

N/A

Section 11.6.4.6

L Offset Rate Limiting

256

N/A

Section 11.6.4.6

M Moving Average Filter

32, 64, 128

Filter

Dependent

Section 11.6.4.7

P Offset Subtraction

32, 64, 128

N/A

Section 11.6.4.6

Q Interpolation

1, 2, 4

tSigChainXX Section 11.6.4.8

R Output Range Selection

1, 2, 4

User Selectable

N/A

Section 11.6.4.9

Table 200. Signal chain diagram legend...continued

11.6.4.1 Decimation sinc filter

The output of the ΣΔ modulator is decimated and converted to a parallel value by a third

order Sinc Filter with a decimation ratio of 16.

(5)

frequency (kHz)

1000

800

400

600

200

aaa-030618

-40

-60

-80

-20

magnitude

(dB)

-100

frequency: 64.08691

magnitude: -96.35657

Figure 23. Sinc filter response 3rd order sinc filter magnitude response

11.6.4.2 Signal trim and compensation

The device includes digital trim to compensate for sensor offset, sensitivity, and non-

linearity over temperature. Equation 6, Equation 7, Equation 8, and Equation 9 are used

for the trim compensation.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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