FXLS93421 datasheet(138/254 Pages) NXP

138 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Response parameters are specified in Section 10 and the offset low-pass filter

coefficients are specified in Table 216.

During startup, multiple phases of the offset low-pass filter are used to allow for fast

convergence of the internal offset error during initialization. The offset rate limiting is also

bypassed regardless of the state of the OC_FILT bits in the CHx_CFG_U4 register. The

low-pass filter details and timing for the startup phases is shown in Table 216.

In normal mode, the offset low-pass filter frequency can be selected and output rate

limiting can be applied to the output of the offset low-pass filter via the OC_FILT bits in

the CHx_CFG_U4 register. Rate limiting can only be enabled if the 0.04 Hz offset LPF is

selected. If rate limiting is enabled, the offset cancellation output is updated by OFFStep

LSB every tRL_Rate seconds.

The offset cancellation circuit output value is frozen when analog or digital self-test is

active (ST_CTRL = 0x8 - 0xF) regard-less of the offset cancellation phase. When analog

or digital self-test is deactivated, the offset cancellation output value freeze is extended

for 15 ms before continuing updates.

Offset LPF

startup phase

Time from reset

to start of phase

(ms)

Sample

Time

(us)

Coefficients (24 bit)

LPF corner

frequency (-3 dB)

(Hz)

Time constant (τ)

(ms)

Rate limiting

0.234051465988159

0.49999988079071

256

1.0

–0.765948414802551

163.8

0.9714

Bypassed

0.063805103302002

0.49999988079071

4.096

256

1.0

–0.936194777488708

40.96

3.886

Bypassed

0.0163367986679077

0.49999988079071

8.192

256

1.0

–0.983663082122802

10.24

15.54

Bypassed

0.00410926342010498

0.49999988079071

24.58

256

1.0

–0.995890617370605

2.560

62.17

Bypassed

0.00102889537811279

0.49999988079071

90.11

256

1.0

–0.998970985412597

0.6400

248.7

Bypassed

0.000257253646850586

0.49999988079071

352.3

256

1.0

–0.999742627143859

0.1600

994.7

Bypassed

0.0000643377478321934

0.49999988079071

1401

256

1.0

–0.9999356623

0.0400

3979

Controlled by

OC_FILT[1:0]

0.000032169

39131789331

n10

0.5

n11

0.5

1401

1024

d10

d11

–0.999967830

25562763214

0.005

32000

Bypassed

Self-test Active

Output Frozen

Table 216. Offset cancellation phases and times: DSI3, SPI, and I2C modes

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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