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CEC1712 Datasheet(PDF) 28 Page - Microchip Technology

Part # CEC1712
Description  Cryptographic Embedded Controller
PDF  338 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

CEC1712 Datasheet(HTML) 28 Page - Microchip Technology

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CEC1712
DS00003416C-page 28
 2020-2021 Microchip Technology Inc.
2.5.2
STRAPPING OPTIONS
GPIO170 is used for the TAP Controller select strap. If any of the JTAG TAP controllers are used, GPIO170 must only
be configured as an output to a VTRx powered external function. GPIO170 may only be configured as an input when
the JTAG TAP controllers are not needed or when an external driver does not violate the Slave Select Timing.See Sec-
tion 32.2.1, "TAP Controller Select Strap Option".
2.6
Pin Default State Through Power Transitions
The power state and power state transitions illustrated in the following tables are defined in Section 4.0, "Power,
Clocks, and Resets". Pin behavior in this table assumes no specific programming to change the pin state. All GPIO
default pins that have the same behavior are described in the table generically as GPIOXXX.
VSS
VTR associated ground
VSS_VBAT
VBAT associated ground
VTR1
VTR Suspend Power Supply
VTR2
Peripheral Power Supply
VTR_PLL
PLL power supply
VTR_REG
Main Regulator Power supply
TABLE 2-5:
STRAP PINS
Pin Name
Strap Name
Strap Define and Value
I/O Power
Rail
GPIO170
JTAG_STRAP
1= Boundary Scan
The JTAG Port is used to access the Boundary scan TAP
controller
0= Normal Operation
The JTAG port is used to access the ARM TAP Controller
VTR1
GPIO104
VTR2_STRAP
Voltage Level strap is used to determine if the Shared
Flash interface must be configured for 3.3V or 1.8V
operation
1= 3.3V Operation
0= 1.8V Operation
VTR1
TABLE 2-6:
PIN DEFAULT STATE THROUGH POWER TRANSITIONS
Signal
VBAT
Applied
VBAT
Stable
VTR
Applied
RESET_
SYS
De-
asserted
RESET_
SYS
Asserted
VTR
Un-
powered
VBAT
Un-
powered
Note
GPIO170
un-
powered
un-
powered
High
In
Z
glitch
un-
powered
GPIOXXX
un-
powered
un-
powered
Z
Z
Z
glitch
un-
powered
Note
D
nRESET_IN
un-
powered
un-
powered
Low
In
Z
glitch
un-
powered
BGPOx
Out=0
Out=0
Retain
Retain
Retain
Retain
un-
powered
Note
B
VCI_INx#
In
In
In
In
In
In
un-
powered
TABLE 2-4:
SIGNAL DESCRIPTION BY INTERFACE (CONTINUED)
SIG_NAME
Description
Notes



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