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CEC1712 Datasheet(PDF) 77 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 77 Page - Microchip Technology |
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77 / 338 page  2020-2021 Microchip Technology Inc. DS00003416C-page 77 CEC1712 4.9.8 PCR POWER RESET STATUS REGISTER Offset 10h Bits Description Type Default Reset Event 31:12 Reserved RES - - 10 32K_ACTIVE 1=The 32K clock input is present. The internal 32K clock is derived from the pin and the ring oscillator is synchronized to the exter- nal 32K clock 0=The 32K clock input is not present. The internal 32K clock is derived from the ring oscillator R- RESET _SYS 9 Reserved RES - - 8 WDT_EVENT This bit allows the application code to determine WDT_EVENT against RESET_VTR R/W1C 0h RESET _SYS- _nWDT 7JTAG_RST# Indicates the JTAG_RST# pin status. The JTAG TRST# input is gated off low when Boundary scan mode is enabled and will not be set in this mode. R- RESET _SYS 6 RESET_SYS_STATUS Indicates the status of RESET_SYS. The bit will not clear if a write 1 is attempted at the same time that a RESET_VTR occurs; this way a reset event is never missed. 1=A reset occurred 0=No reset occurred since the last time this bit was cleared R/WC 1h RESET _SYS 5 VBAT_RESET_STATUS Indicates the status of RESET_VBAT. The bit will not clear if a write of ‘1’b is attempted at the same time that a VBAT_RST_N occurs, this way a reset event is never missed. 1=A reset occurred 0=No reset occurred while VTR_CORE was off or since the last time this bit was cleared R/WC - RESET _SYS 4 RESET_VTR_STATUS Indicates the status of RESET_VTR event. R/W1C 1h RESET _VTR Note 1: This read-only status bit always reflects the current status of the event and is not affected by any Reset events. |
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