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CEC1712 Datasheet(PDF) 10 Page - Microchip Technology

Part # CEC1712
Description  Cryptographic Embedded Controller
PDF  338 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

CEC1712 Datasheet(HTML) 10 Page - Microchip Technology

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CEC1712
DS00003416C-page 10
 2020-2021 Microchip Technology Inc.
2.0
PIN CONFIGURATION
2.1
Description
The Pin Configuration chapter includes Pin List, Pin Multiplexing.
2.2
Terminology and Symbols for Pins/Buffers
2.2.1
BUFFER TERMINOLOGY
2.2.2
PIN NAMING CONVENTIONS
• Pin Name is composed of the multiplexed options separated by ‘/’. E.g., GPIOxxxx/SignalA/SignalB.
• The first signal shown in a pin name is the default signal. E.g., GPIOxxxx/SignalA/SignalB means the GPIO is the
default signal.
• Parenthesis ‘()’ are used to list aliases or alternate functionality for a single mux option.
• Square brackets ‘[ ]’ are used to indicate there is a Strap Option on a pin. This is always shown as the last signal
on the Pin Name.
• Signal Names appended with a numeric value indicates the Instance Number. E.g., PWM0, PWM1, etc. indicates
that PWM0 is the PWM output for PWM Instance 0, PWM1 is the PWM output for PWM Instance 1, etc. The
instance number may be omitted if there in only one instance of the IP block implemented.
2.3
Pin List
TABLE 2-1:
CEC1712 PIN MAP
Term
Definition
#
The ‘#’ sign at the end of a signal name indicates an active-low signal
n
The lowercase ‘n’ preceding a signal name indicates an active-low signal
PWR
Power
PIO
Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output. Configurable drive strength from 2ma to12ma.
Note:
All GPIOs have programmable drive strength options of 2ma, 4ma, 8ma and 12ma.
GPIO pin drive strength is determined by the Pin Control Register Defaults field in
the Pin Control Register 2.
In
I Type Input Buffer.
O2
O-2 mA Type Buffer.
PECI
PECI Input/Output. These pins operate at the processor voltage level (VREF_VTT)
SB-TSI
SB-TSI Input/Output. These pins operate at the processor voltage level (VREF_VTT)
Ball map
Signal
D2
nRESET_IN
F3
GPIO057/VCC_PWRGD
E2
GPIO106/PWROK
B2
GPIO051/ICT1_TACH1
A3
GPIO050/ICT0_TACH0
F2
GPIO200/ADC00/TRACEDAT0
G2
GPIO201/ADC01/TRACEDAT1
H2
GPIO202/ADC02/TRACEDAT2
G1
GPIO203/ADC03/TRACEDAT3
H1
GPIO204/ADC04



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