CEC1712 datasheet(13/338 Pages) MICROCHIP

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DS00003416C-page 13

CEC1712

2.4.3

BUFFER TYPES

The Buffer Type column defines the type of Buffer associated with each signal. Some pins have signals with two different

buffer types sharing the pin; in this case, table shows the buffer type for each of the signals that share the pin.

Input signals muxed with GPIOs are marked as “I”

Output signals muxed with GPIOs are marked as “PIO”, because the GPIO input path is always active even when the

alternate function selected is “output only”. So the GPIO input can be read to see the level of the output signal.

Pad Types are defined in the Section 33.0, "Electrical Specifications," on page 306.

• I/O Pad Types are defined in Section 33.2.4, "DC Electrical Characteristics for I/O Buffers," on page 308.

• The abbreviation “PWR” is used to denote power pins. The power supplies are defined in Section 33.2.1, "Power

Supply Operational Characteristics," on page 306.

2.4.4

GLITCH PROTECTION

Pins with glitch protection are glitch-free tristate pins and will not drive out while their associated power rail is rising.

These glitch-free tristate pins require either an external pull-up or pull-down to set the state of the pin high or low.

All pins are glitch protected.

2.4.5

OVER-VOLTAGE PROTECTION

If a pin is over-voltage protected (over-voltage protection = YES) then the following is true: If the pad is powered by 1.8V

+/- 5% (operational) it can tolerate up to 3.63V on the pad. This allows for a pull-up to 3.3V power rail +/- 10%. If the

pad is powered by 3.3V +/- 5% (operational) it can tolerate up to 5.5V on the pad. This allows for a pull-up to 5.0V power

rail +/- 10%.

If a pin is not over-voltage protected (over-voltage protection = NO) then the following is true: If the pad is powered by

1.8V +/- 5% (operational), it can tolerate up to 1.8V +10% (i.e., +1.98V max). If the pad is powered by 3.3V +/- 5% (oper-

ational) it can tolerate up to 3.3V +10% (i.e., +3.63V max).

2.4.6

UNDER-VOLTAGE PROTECTION

Pins that are identified as having Under-voltage PROTECTION may be configured so they will not sink excess current

if powered by 3.3V and externally pulled up to 1.8V. The following configuration requirements must be met.

• If the pad is an output only pad type and it is configured as either open drain or the output is disabled.

• If the pin is a GPIO pin with a PIO pad type then is must be configured as open drain output with the input dis-

abled. The input is disabled by setting the GPIO Power Gating Signals (PGS) bits to 11b.

All pins are under voltage protected.

2.4.7

BACKDRIVE PROTECTION

Assuming that the external voltage on the pin is within the parameters defined for the specific pad type, the backdrive

protected pin will not sink excess current when it is at a lower potential than the external circuit. There are two cases

where this occurs:

• The pad power is off and the external circuit is powered

• The pad power is on and the external circuitry is pulled to a higher potential than the pad power. This may occur

on 3.3V powered pads that are 5V tolerant or on 1.8V powered pads that are 3.6V tolerant.

2.4.8

EMULATED POWER WELL

Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating

Signals (PGS) option in the GPIO Pin Control Register. The Emulated Power Well column in the Pin Multiplexing table

defines the power gating programming options supported for each signal.

Note:

If the pin needs to default low, a 1M ohm (max) external pull-down is required.

Note:

The power rail must rise monotonically in order for glitch protection to operate.

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