CEC1712 datasheet(81/338 Pages) MICROCHIP

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CEC1712

5.3

Terminology

5.3.1

ARM IP TERMS AND ACRONYMS

•AHB

Advanced High-Performance Bus, a system-level on-chip AMBA 2 bus standard. See Reference[5], ARM Lim-

ited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999.

•AHB-AP

AHB Access Port, the AP option selected by Microchip for the DAP

• AHB-Lite

A Single-Master subset of the AHB bus standard: defined in the AMBA 3 bus standard. See Reference[6], ARM

Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006.

•AMBA

The collective term for bus standards originated by ARM Limited.

AMBA 3 defines the IP’s AHB-Lite and ATB bus interfaces.

AMBA 2 (AMBA Rev. 2.0) defines the EC’s AHB bus interface.

•AP

Any of the ports on the DAP subblock for accessing on-chip resources on behalf of the Debugger, independent

of processor operations. A single AHB-AP option is currently selected for this function.

• APB

Advanced Peripheral Bus, a limited 32-bit-only bus defined in AMBA 2 for I/O register accesses. This term is

relevant only to describe the PPB bus internal to the EC core. See Reference [5], ARM Limited: AMBA® Speci-

fication (Rev 2.0), IHI0011A, 13 May 1999.

• ARMv7

The identifying name for the general architecture implemented by the Cortex-M family of IP products.

The ARMv7 architecture has no relationship to the older “ARM 7” product line, which is classified as an “ARMv3”

architecture, and is very different.

•ATB

Interface standard for Trace data to the TPIU from ETM and/or ITM blocks, Defined in AMBA 3. See Refer-

ence[7], ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006.

• Cortex-M4

The ARM designation for the specific IP selected for this product: a Cortex M4 processor core

•DAP

Debug Access Port, a subblock consisting of DP and AP subblocks.

•DP

Any of the ports in the DAP subblock for connection to an off-chip Debugger. A single SWJ-DP option is currently

selected for this function, providing JTAG connectivity.

•DWT

Data Watchdog and Trace subblock. This contains comparators and counters used for data watchpoints and

Core activity tracing.

•ETM

Embedded Trace Macrocell subblock. Provides enhancements for Trace output reporting, mostly from the DWT

subblock. It adds enhanced instruction tracing, filtering, triggering and timestamping.

•FPB

FLASH Patch Breakpoint subblock. Provides either Remapping (Address substitution) or Breakpointing (Excep-

tion or Halt) for a set of Instruction addresses and Data addresses. See Section 8.3 of Reference [1], ARM Lim-

ited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010.

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