CEC1712 datasheet(65/338 Pages) MICROCHIP

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 2020-2021 Microchip Technology Inc.

DS00003416C-page 65

CEC1712

4.0

POWER, CLOCKS, AND RESETS

4.1

Introduction

The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies, clock sources, and reset inputs to the

chip and defines all the derived power, clock, and reset signals. In addition, this section identifies Power, Clock, and

Reset events that may be used to generate an interrupt event, as well as, the Chip Power Management Features.

4.2

References

No references have been cited for this chapter.

4.3

Interrupts

The Power, Clocks, and Resets logic generates no events

4.4

Power

TABLE 4-1:

POWER SOURCE DEFINITIONS

Power Well

Nominal

Voltage

Description

Source

VTR_REG

1.8V - 3.3V

This supply is used to derive the chip’s

core power.

Pin Interface

VTR_ANALOG

3.3V

3.3V Analog Power Supply.

VTR_PLL

3.3V

3.3V Power Supply for the 48MHz PLL.

This must be connected to the same

supply as VTR_ANALOG.

Pin Interface

VTR1

3.3V

3.3V System Power Supply.

This is typically connected to the

“Always-on” or “Suspend” supply rails

in system. This supply must be on prior

to the system RSMRST# signal being

deasserted

Pin Interface

VTR2

3.3V or 1.8V

3.3V or 1.8V System Power Supply.

This supply is used to power one bank

of I/O pins. See Note 1.

Pin Interface

VTR_CORE

1.2V

The main power well for internal logic

Internal regulator

VBAT

3.0V - 3.3V

System Battery Back-up Power Well.

This is the “coin-cell” battery.

GPIOs that share pins with VBAT sig-

nals are powered by this supply.

Pin Interface

VBAT

VSS

Digital Ground

Pin Interface

Note 1: See Section 4.4.1, "I/O Rail Requirements" for connection requirements for VTRx.

2: The source for the Internal regulator is VTR_REG.

3: VTR refers to VTR_REG and VTR_ANALOG.

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