CEC1712 datasheet(70/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 70

 2020-2021 Microchip Technology Inc.

RESET_SYS

Internal Reset signal. This signal is used to reset

VTR_CORE powered registers.

RESET_SYS is the main global reset signal.

This reset signal will be asserted if:

• RESET_VTR is asserted

• The nRESET_IN pin asserted

•A WDT Event event is asserted

• A soft reset is asserted by the SOFT_SYS-

_RESET bit in the System Reset Register

• ARM M4 SYSRESETREQ

RESET_VCC

Performs a reset when Host power (VCC) is

turned off

This signal is asserted if

Note:

RESET_SYS is asserted

RESET_HOST

Performs a reset when VCC_PWRGD is low

This signal is asserted if

• RESET_SYS is asserted

• VCC_PWRGD is low

•The PWR_INV bit in the Power Reset Con-

trol Register is ‘1b’1

WDT Event

A WDT Event generates the RESET_SYS

event. This signal resets VTR_CORE powered

registers with the exception of the WDT Event

Count Register register. Note that the glitch pro-

tect circuits do not activate on a WDT reset.

WDT Event does not reset VBAT registers or

logic.

This reset signal will be asserted if:

•A WDT Event event is asserted

This event is indicated by the WDT bit in the

Power-Fail and Reset Status Register

RESET_SYS_n

WDT

Internal Reset signal. This signal is used to reset

VTR_CORE powered registers not effected by a

WDT Event

A RESET_SYS_nWDT is used to reset registers

that need to be preserved through a WDT Event

like a WDT Event Count Register.

This reset signal will be asserted if:

• RESET_VTR is asserted

• The nRESET_IN pin asserted

RESET_EC

Internal reset signal to reset the processor in the

EC Subsystem.

This reset is a stretched version of

RESET_SYS. This reset asserts at the same

time that RESET_SYS asserts and is held

asserted for 1ms after RESET_SYS deasserts.

RESET_BLOCK

Each IP block in the device may be configured to

be reset by setting the RESET_ENABLE regis-

ter.

This reset signal will be asserted if Block N

RESET_ENABLE is set to 1 and Peripheral

Reset Enable n Register is unlocked.

TABLE 4-6:

DEFINITION OF RESET SIGNALS (CONTINUED)

Reset

Description

Source

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