CEC1712 datasheet(71/338 Pages) MICROCHIP

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DS00003416C-page 71

CEC1712

FIGURE 4-3:

RESETS BLOCK DIAGRAM

4.7

Chip Power Management Features

This device is designed to always operate in its lowest power state during normal operation. In addition, this device

offers additional programmable options to put individual logical blocks to sleep as defined in the following section,

Section 4.7.1.

4.7.1

BLOCK LOW POWER MODES

All power related control signals are generated and monitored centrally in the chip’s Power, Clocks, and Resets (PCR)

block. The power manager of the PCR block uses a sleep interface to communicate with all the blocks. The sleep inter-

face consists of three signals:

• SLEEP_ENABLE (request to sleep the block) is generated by the PCR block. A group of SLEEP_ENABLE sig-

nals are generated for every clock segment. Each group consists of a SLEEP_ENABLE signal for every block in

that clock segment.

• CLOCK_REQUIRED (request clock on) is generated by every block. They are grouped by blocks on the same

clock segment. The PCR monitors these signals to see when it can gate off clocks.

A block can always drive CLOCK_REQUIRED low synchronously, but it must drive it high asynchronously since its inter-

nal clocks are gated and it has to assume that the clock input itself is gated. Therefore the block can only drive

CLOCK_REQUIRED high as a result of a register access or some other input signal.

RESET_VTR

SOFT_SYS_RESET

TEST_VTR_RESET

RESET_SYS

VCC_PWRGD

RESET_HOST

Note 1: SOFT_SYS_RESET is implemented in bit[8] of the System Reset Register

Note 2: PWR_INV is implemented in bit[0] of the Power Reset Control Register

Note 3: TEST_VTR_RESET is implemented in bit [1] of the Host Global Test Register

1ms

Delay

RESET_EC

RESETI

PWROK

PWR_INV

RESET_VCC

PWR_INV

WDT

CORTEXM4_RESET

Reset

Enable

RESET_SYS_nWDT

E.g. WDT Event Count

RESET_BLOCK_N

WDT_Event

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