CEC1712 datasheet(88/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 88

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5.10.1

DEBUG AND ACCESS PORTS (SWJ-DP AND AHB-AP SUBBLOCKS)

These two subblocks work together to provide access to the chip for the Debugger using the Debug JTAG connection,

as described in Chapter 4 of the ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 Feb-

ruary 2006.

5.10.2

BREAKPOINT, WATCHPOINT AND TRACE SUPPORT

See References [11], ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006

and [12], ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-

008772, 17 August 2009. A summary of functionality follows.

Breakpoint and Watchpoint facilities can be programmed to do one of the following:

• Halt the processor. This means that the external Debugger will detect the event by periodically polling the state of

the EC.

• Transfer control to an internal Debug Monitor firmware routine, by triggering the Debug Monitor exception (see

Table 5-4, "Exception and Interrupt Vector Table Layout").

5.10.2.1

Instrumentation Support (ITM Subblock)

The Instrumentation Trace Macrocell (ITM) is for profiling software. This uses non-blocking register accesses, with a

fixed low-intrusion overhead, and can be added to a Real-Time Operating System (RTOS), application, or exception

handler. If necessary, product code can retain the register access instructions, avoiding probe effects.

5.10.2.2

HW Breakpoints and ROM Patching (FPB Subblock)

The Flash Patch and Breakpoint (FPB) block. This block can remap sections of ROM, typically Flash memory, to regions

of RAM, and can set breakpoints on code in ROM. This block can be used for debug, and to provide a code or data

patch to an application that requires field updates to a product in ROM.

5.10.2.3

Data Watchpoints and Trace (DWT Subblock)

The Debug Watchpoint and Trace (DWT) block provides watchpoint support, program counter sampling for performance

monitoring, and embedded trace trigger control.

5.10.2.4

Trace Interface (ETM and TPIU)

The Embedded Trace Macrocell (ETM) provides instruction tracing capability. For details of functionality and usage, see

References [13], ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification,

IHI0014Q, 23 September 2011 and [14], ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual,

DDI0440C, 29 June 2010.

The Trace Port Interface Unit (TPIU) provides the external interface for the ITM, DWT and ETM.

TABLE 5-5:

ARM JTAG ID

ARM Debug Mode

JTAG ID

SW-DP (2-wire)

0x2BA01477

JTAG (4-wire)

0x4BA00477

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