CEC1712 datasheet(100/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 100

 2020-2021 Microchip Technology Inc.

7.12.3

DMA CHANNEL N ACTIVATE REGISTER

18h

DMA Channel N Interrupt Enable Register

1Ch

TEST

20h

(Note 2)

DMA Channel N CRC Enable Register

24h

(Note 2)

DMA Channel N CRC Data Register

28h

(Note 2)

DMA Channel N CRC Post Status Register

2Ch

(Note 2)

TEST

20h

(Note 3)

DMA Channel N Fill Enable Register

24h

(Note 3)

DMA Channel N Fill Data Register

28h

(Note 3)

DMA Channel N Fill Status Register

2Ch

(Note 3)

TEST

Offset

00h

Bits

Description

Type

Default

Reset

Event

7:1 Reserved

RES

0 CHANNEL_ACTIVATE

Enable this channel for operation.

The DMA Main Control:Activate must also be enabled for this chan-

nel to be operational.

R/W

RESET

TABLE 7-10:

CHANNEL REGISTER SUMMARY (CONTINUED)

Offset

(Note 1)

Note 1: The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel

implemented will have these registers to determine that channel’s operation.

2: These registers are only present on DMA Channel 0. They are reserved on all other

channels.

3: These registers are only present on DMA Channel 1. They are reserved on all other

channels.

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