CEC1712 datasheet(75/338 Pages) MICROCHIP

75 / 338 page

 2020-2021 Microchip Technology Inc.

DS00003416C-page 75

CEC1712

4.9.4

SYSTEM SLEEP CONTROL REGISTER

Offset

Bits

Description

Type

Default

Reset

Event

31:9

Reserved

RES

SLEEP_IMMEDIATE

0 = System will only allow entry into sleep after PLL locks.

1 = System will allow entry into Heavy Sleep before PLL locks.

Heavy Sleep : Any sleep state where the PLL is OFF.

Light Sleep : Any sleep state where the PLL is ON.

R/W

RESET

_SYS

7:4

Reserved

RES

SLEEP_ALL

By setting this bit to ‘1b’ and then issuing a WAIT FOR INTER-

RUPT instruction, the EC can initiate the System Sleep mode.

When no device requires the main system clock, the system enters

the sleep mode defined by the field SLEEP_MODE.

This bit is automatically cleared when the processor vectors to an

interrupt.

1=Assert all sleep enables

0=Do not sleep all

R/W

RESET

_SYS

TEST

Test bit. Should always be written with a ‘0b’.

R/W

RESET

_SYS

Reserved

RES

SLEEP_MODE

Sleep modes differ only in the time it takes for the 48MHz clock

domain to lock to 48MHz. The wake latency in all sleep modes is

0ms. Table 4-9 shows the time to lock latency for the different sleep

modes.

1=Heavy Sleep

0=Light Sleep

R/W

RESET

_SYS

TABLE 4-9:

SYSTEM SLEEP MODES

SLEEP_MODE

Sleep State

Latency to

Lock

Description

LIGHT SLEEP

Output of the PLL is gated in sleep. The PLL remains on.

HEAVY SLEEP

3ms

The PLL is shut down while in sleep.

CEC1712 Datasheet(PDF) 75 Page - Microchip Technology

CEC1712 Datasheet(HTML) 75 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL