CEC1712 datasheet(93/338 Pages) MICROCHIP

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DS00003416C-page 93

CEC1712

7.4

Interface

This block is designed to be accessed internally via a registered host interface.

7.5

Signal interface

This block doesn’t have any external signals that may be routed to the pin interface. This DMA Controller is intended to

be used internally to transfer large amounts of data without the embedded controller being actively involved in the trans-

fer.

7.6

Host Interface

The registers defined for the Internal DMA Controller are accessible by the various hosts as indicated in Section 3.2,

"Block Overview and Base Addresses".

7.7

DMA Interface

Each DMA Master Device that may engage in a DMA transfer must have a compliant DMA interface. The following table

lists the DMA Devices in the CEC1712.

FIGURE 7-1:

INTERNAL DMA CONTROLLER I/O DIAGRAM

TABLE 7-2:

DMA CONTROLLER DEVICE SELECTION

Device Name

Device Number

(Note 1)

Controller Source

SMB-I2C 0 Controller

Slave

1Master

SMB-I2C 1 Controller

Slave

3Master

SMB-I2C 2 Controller

Slave

5Master

SMB-I2C 3 Controller

Slave

7Master

SMB-I2C 4Controller

Transmit

9Receive

Note 1: The Device Number is programmed into field HARDWARE_FLOW_CONTROL_DEVICE of the DMA

Channel N Control Register register.

Internal DMA Controller

Power, Clocks and Reset

Interrupts

DMA Interface

Host Interface

Signal interface

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