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CEC1712 Datasheet(PDF) 104 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 338 page  CEC1712 DS00003416C-page 104 2020-2021 Microchip Technology Inc. 7.12.8 DMA CHANNEL N INTERRUPT STATUS REGISTER 7.12.9 DMA CHANNEL N INTERRUPT ENABLE REGISTER Offset 14h Bits Description Type Default Reset Event 7:3 Reserved RES - - 2 STATUS_DONE This is an interrupt source register. This flags when the DMA Channel has completed a transfer suc- cessfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address. A completion due to a Hardware Flow Control Terminate will not flag this interrupt. 1=MEMORY_START_ADDRESS equals MEMORY_END_AD- DRESS 0=MEMORY_START_ADDRESS does not equal MEMO- RY_END_ADDRESS R/WC 0h RESET 1 STATUS_ENABLE_FLOW_CONTROL This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA. 1=Hardware Flow Control is requesting after the transfer has com- pleted 0=No Hardware Flow Control event R/WC 0h RESET 0 STATUS_BUS_ERROR This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1=Error detected. R/WC 0h RESET Offset 18h Bits Description Type Default Reset Event 7:3 Reserved RES - - 2 STATUS_ENABLE_DONE This is an interrupt enable for STATUS_DONE. 1=Enable Interrupt 0=Disable Interrupt R/W 0h RESET 1 STATUS_ENABLE_FLOW_CONTROL_ERROR This is an interrupt enable for STATUS_ENABLE_FLOW_CON- TROL. 1=Enable Interrupt 0=Disable Interrupt R/W 0h RESET |
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