CEC1712 datasheet(108/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 108

 2020-2021 Microchip Technology Inc.

8.0

EC INTERRUPT AGGREGATOR

8.1

Introduction

The EC Interrupt Aggregator works in conjunction with the processor’s interrupt interface to handle hardware interrupts

and exceptions.

Exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts. All three excep-

tions - reset, memory error, and instruction error - are hardwired directly to the processor. Interrupts are typically asyn-

chronous and are maskable.

Interrupts classified as wake events can be recognized without a running clock, e.g., while the CEC1712 is in sleep

state.

This chapter focuses on the EC Interrupt Aggregator. Please refer to embedded controller’s documentation for more

information on interrupt and exception handling.

8.2

Interface

This block is designed to be accessed internally via a registered host interface. The following diagram illustrates the

various interfaces to the block.

8.3

Signal Description

8.3.1

SIGNAL INTERFACE

There are no external signals for this block.

FIGURE 8-1:

EC INTERRUPT AGGREGATOR INTERFACE DIAGRAM

EC Interrupt Aggregator

Signal Interface

Power, Clocks and Reset

Host Interface

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