CEC1712 datasheet(110/338 Pages) MICROCHIP

110 / 338 page

CEC1712

DS00003416C-page 110

 2020-2021 Microchip Technology Inc.

8.8.1

AGGREGATED INTERRUPTS

All interrupts are routed to the ARM processor through the ARM Nested Vectored Interrupt Controller (NVIC). As shown

in Figure 8-2, "Interrupt Structure", all interrupt sources are aggregated into the GIRQx Source registers. In many cases,

the Result bit for an individual interrupt source is tied directly to the NVIC. These interrupts are shown in the “Direct

NVIC” column in the Interrupt Bit Assignments table. In addition, all GIRQx can also generate an interrupt to the NVIC

when any of the enabled interrupts in its group is asserted. The NVIC vectors for the aggregated GIRQ interrupts are

shown tin the “Agg NVIC” column.

Firmware should not enable the group GIRQ NVIC interrupt at the same time individual direct interrupts for members of

the group are enabled. If both are enabled, the processor will receive two interrupts for an event, one from the GIRQ

and one from the direct interrupt.

FIGURE 8-2:

INTERRUPT STRUCTURE

Note:

The four Soft Interrupts that are defined by the RTOS Timer do not have individual NVIC vectors. If the use

of the SWI interrupts is required, then all interrupts in the GIRQ must disable the individual NVIC vectors.

Note:

These four Soft Interrupts are only available in aggregate mode

SOURCE0

ENABLE0

Int source

Int enable

SOURCE1

SOURCEn

ENABLE1

ENABLEn

Interrupt

from block

NVIC

Inputs for

blocks

GIRQx

Block Enable

NVIC

Input for

GIRQx

Bit x

Interrupt

from block

Interrupt

from block

NVIC_EN

result

To Wake

Interface

Asynchronous Interrupt from

blocks w/ Wake Capability

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