CEC1712 datasheet(111/338 Pages) MICROCHIP

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DS00003416C-page 111

CEC1712

8.8.2

WAKE GENERATION

Wake-capable interrupts are listed in Table 3-3, "GIRQ_mapping" with a designation of ‘Yes’ in the Wake Event column.

All interrupts, except GIRQ22, generate an EC Interrupt event. They are routed to source bits that are synchronized to

the 32 MHz Ring Oscillator. If enabled, the Interrupt Result is fed into the Priority Encoder/Decision Logic, which gen-

erates the interrupt vector to the NVIC Interrupt Interface.

Some Interrupts, which are labeled Wake-Capable, are also routed as Wake Events to the Chip’s Wake Logic. These

are asynchronous events that are used to resume the 32 MHz Ring Oscillator operation from a sleep state and wake

the processor.

8.8.2.1

Wake Capable Interrupts

All GPIO inputs are wake-capable. In order for a GPIO input to wake the CEC1712 from a sleep state, the Interrupt

Detection field of the GPIO Pin Control Register must be set to Rising Edge Triggered, Falling Edge Triggered, or Either

Edge Triggered. If the Interrupt Detection field is set to any other value, a GPIO input will not trigger a wake interrupt.

Some of the Wake Capable Interrupts are triggered by activity on pins that are shared with a GPIO. These interrupts will

only trigger a wake if the Interrupt Detection field of the corresponding GPIO Pin Control Register is set to Rising Edge

Triggered, Falling Edge Triggered, or Either Edge Triggered.

8.8.2.2

Wake-Only Events

Some devices which respond to an external master require the 48MHz clock domain to operate but do not necessarily

require and immediate processing by the EC. Wake-only events provide the means to start the 48MHz clock domain

without triggering an EC interrupt service routine. This events are grouped into a single GIRQ, GIRQ22. Events that are

enabled in that GIRQ will start the clock domain when the event occurs, but will not invoke an EC interrupt. The

SLEEP_ENABLE flags all remain asserted. If the activity for the event does not in turn trigger another EC interrupt, the

CLOCK_REQUIRED for the block will re-assert and the configured sleep state will be re-entered.

8.8.3

INTERRUPT SUMMARY

Interrupt bit assignments, including wake capabilities and NVIC vector locations, are shown in the Interrupt Aggregator

Bit Assignments Table in Section 3.0, "Device Inventory". The table lists all possible interrupt sources; the register bits

for any interrupt source, such as a GPIO, that is not implemented in a particular part are reserved.

8.8.4

DISABLING INTERRUPTS

The Block Enable Clear Register and Block Enable Set Register should not be used for disabling and enabling interrupts

for software operations i.e., critical sections. The ARM enable disable mechanisms should be used.

8.9

EC Registers

Registers for this block are shown in the following summary table. Addresses for each register are determined by adding

the offset to the Base Address for of the EC Interrupt Aggregator Block in the Block Overview and Base Address Table

in Section 3.0, "Device Inventory".

TABLE 8-4:

Offset

00h

GIRQ8 Source Register

04h

GIRQ8 Enable Set Register

08h

GIRQ8 Result Register

0Ch

GIRQ8 Enable Clear Register

10h

Reserved

14h

GIRQ9 Source Register

18h

GIRQ9 Enable Set Register

1Ch

GIRQ9 Result Register

20h

GIRQ9 Enable Clear Register

24h

Reserved

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