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CEC1712 Datasheet(PDF) 113 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 113 Page - Microchip Technology |
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113 / 338 page  2020-2021 Microchip Technology Inc. DS00003416C-page 113 CEC1712 All of the GIRQx Source, Enable Set, Enable Clear and Result registers have the same format. The following tables define the generic format for each of these registers. The bit definitions are defined in the sections that follow. D8h Reserved DCh GIRQ19 Source Register E0h GIRQ19 Enable Set Register E4h GIRQ19 Result Register E8h GIRQ19 Enable Clear Register ECh Reserved F0h GIRQ20 Source Register F4h GIRQ20 Enable Set Register F8h GIRQ20 Result Register FCh GIRQ20 Enable Clear Register 100h Reserved 104h GIRQ21 Source Register 108h GIRQ21 Enable Set Register 10Ch GIRQ21 Result Register 110h GIRQ21 Enable Clear Register 114h Reserved 118h GIRQ22 Source Register 11Ch GIRQ22 Enable Set Register 120h GIRQ22 Result Register 124h GIRQ22 Enable Clear Register 128h Reserved 12Ch GIRQ23 Source Register 130h GIRQ23 Enable Set Register 134h GIRQ23 Result Register 138h GIRQ23 Enable Clear Register 13Ch Reserved 140h GIRQ24 Source Register 144h GIRQ24 Enable Set Register 148h GIRQ24 Result Register 14Ch GIRQ24 Enable Clear Register 150h Reserved 154h GIRQ25 Source Register 158h GIRQ25 Enable Set Register 15Ch GIRQ25 Result Register 160h GIRQ25 Enable Clear Register 164h Reserved 168h GIRQ26 Source Register 16Ch GIRQ26 Enable Set Register 170h GIRQ26 Result Register 174h GIRQ26 Enable Clear Register 200h Block Enable Set Register 204h Block Enable Clear Register 208h Block IRQ Vector Register TABLE 8-4: REGISTER SUMMARY (CONTINUED) Offset Register Name |
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