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CEC1712 Datasheet(PDF) 116 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 116 Page - Microchip Technology |
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116 / 338 page ![]() CEC1712 DS00003416C-page 116 2020-2021 Microchip Technology Inc. 8.9.6 BLOCK ENABLE CLEAR REGISTER 8.9.7 BLOCK IRQ VECTOR REGISTER 26:8 IRQ_VECTOR_ENABLE_SET Each bit in this field enables the group GIRQ interrupt assertion to the NVIC. 1=Interrupts in the GIRQx Source Register may be enabled 0=No effect R/WS 0h RESET _SYS 7:0 Reserved RES - - Offset 204h Bits Description Type Default Reset Event 31:27 Reserved RES - - 26:8 IRQ_VECTOR_ENABLE_CLEAR Each bit in this field disables the group GIRQ interrupt assertion to the NVIC. 1=Interrupts in the GIRQx Source Register are disabled 0=No effect R/WC 0h RESET _SYS 7:0 Reserved RES - - Offset 208h Bits Description Type Default Reset Event 31:27 Reserved RES 0h - 26:8 IRQ_VECTOR Each bit in this field reports the status of the group GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt is disabled as a group, by the Block Enable Clear Register, then the corresponding bit will be ‘0’b and no interrupt will be asserted. R0h RESET _SYS 7:0 Reserved RES 0h - Offset 200h Bits Description Type Default Reset Event |
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