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CEC1712 Datasheet(PDF) 106 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 106 Page - Microchip Technology |
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106 / 338 page  CEC1712 DS00003416C-page 106 2020-2021 Microchip Technology Inc. 7.12.11 DMA CHANNEL N CRC DATA REGISTER 7.12.12 DMA CHANNEL N CRC POST STATUS REGISTER Offset 24h Bits Description Type Default Reset Event 31:0 CRC Writes to this register initialize the CRC generator. Reads from this register return the output of the CRC that is calculated from the data transfered by DMA Channel N. The output of the CRC gener- ator is bit-reversed and inverted on reads, as required by the CRC- 32-IEEE definition. A CRC can be accumulated across multiple DMA transactions on Channel N. If it is necessary to save the intermediate CRC value, the result of the read of this register must be bit-reversed and inverted before being written back to this register. R/W 0h RESET Offset 28h Bits Description Type Default Reset Event 31:4 Reserved RES - - 3 CRC_DATA_READY This bit is set to ‘1b’ when the DMA controller is processing the post-transfer of the CRC data. This bit is cleared to ‘0b’ when the post-transfer completes. R0h RESET 2 CRC_DATA_DONE This bit is set to ‘1b’ when the DMA controller has completed the post-transfer of the CRC data. This bit is cleared to ‘0b’ when the a new DMA transfer starts. R0h RESET 1 CRC_RUNNING This bit is set to ‘1b’ when the DMA controller starts the post-trans- fer transmission of the CRC. It is only set when the post-transfer is enabled by the CRC_POST_TRANSFER_ENABLE field. This bit is cleared to ‘0b’ when the post-transfer completes. R0h RESET 0 CRC_DONE This bit is set to ‘1b’ when the CRC calculation has completed from either normal or forced termination. It is cleared to ‘0b’ when the DMA controller starts a new transfer on the channel. R0h RESET |
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