TPS25751D datasheet(19/89 Pages) TI1

19 / 89 page

6.19 I2C Requirements and Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Capacitive load for each bus line

(external)

400

SDA and SCL Standard Mode Characteristics (Target)

fSCLS

Clock frequency for target

VDD = 1.8 V or 3.3 V

100

kHz

tVD;DAT

Valid data time

Transmitting Data, VDD = 1.8 V or

3.3 V, SCL low to SDA output valid

3.45

µs

tVD;ACK

Valid data time of ACK condition

Transmitting Data, VDD = 1.8 V or

3.3 V, ACK signal from SCL low to

SDA (out) low

3.45

µs

SDA and SCL Fast Mode Characteristics (Target)

fSCLS

Clock frequency for target

VDD = 1.8 V or 3.3 V

100

400

kHz

tVD;DAT

Valid data time

Transmitting data, VDD = 1.8 V,

SCL

low to SDA output valid

0.9

µs

tVD;ACK

Valid data time of ACK condition

Transmitting data, VDD = 1.8 V or

3.3 V, ACK

signal from SCL low to SDA (out)

low

0.9

µs

fSCLS

Clock frequency for Fast Mode

Plus(1)

VDD = 1.8 V or 3.3 V

400

800

kHz

tVD;DAT

Valid data time

Transmitting data, VDD = 1.8 V or

3.3 V, SCL

low to SDA output valid

0.55

µs

tVD;ACK

Valid data time of ACK condition

Transmitting data, VDD = 1.8 V or

3.3 V, ACK

signal from SCL low to SDA (out)

low

0.55

µs

tLOW

Clock low time

VDD = 3.3 V

1.3

µs

tHIGH

Clock high time

VDD = 3.3 V

0.6

µs

(1)

Controller must control fSCLS to ensure tLOW > tVD; ACK.

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TPS25751

SLVSH93 – OCTOBER 2023

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