TPS25751D datasheet(71/89 Pages) TI1

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Figure 9-40. TPS25751S PCB Layout - Bottom Layer

9.4.2.2.2.1 TPS25751S Component Placement

LDO_1V5 (pin 4), LDO_3V3 (pin 1), and VIN_3V3 (pin 32)

The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to

be placed as close as possible to TPS25751S device for optimal performance. For this example to minimize

solution size, the decoupling capacitors are placed on the bottom layer with their ground pads directly

underneath the ground pad of TPS25751S. Use a maximum of one via per pin from TPS25751S to the

decoupling capacitors if placed on a different layer. Use a minimum of 10mil trace width to route these three

traces, preferably with 16mil trace width if possible.

CC1 (pin 24) and CC2 (pin 25)

CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the

same layer as the TPS25751S device. When routing the CCx traces, DO NOT via to another layer in between

the CCx pins of the TPS25751S to the CCx capacitors. Check to make sure the CCx capacitors are not place

outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads

as shown in the example layout (refer to figure 10-21). Use a minimum of 10mil trace width to ensure Vconn

support (5V/0.6A).

9.4.2.2.2.2 TPS25751S PP5V

The 10uF decoupling capacitor (C8) need to be placed as close as possible to the PP5V pins of TPS25751S.

DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A for

sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 28 and 29) to the 5V power plane, use a

minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle necks cause

by other vias or traces, large bottle necks reduces the efficiency of the power plane. The bulk capacitors (C6,

C7, and C9) represent capacitances from the system 5V rail, these are placed further away from TPS25751S on

the same PP5V power plane. Refer to figure 10-21 and figure 10-22 for placement and trace reference.

9.4.2.2.2.3 TPS25751S PP_EXT

Place the PP_EXT decoupling capacitors (C12, C13, and C14) as close as possible to TPS25751S, these do

not need to be on the same layer as the device. The PP_EXT power plane needs to be sized to support up to

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TPS25751

SLVSH93 – OCTOBER 2023

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TPS25751D Datasheet(PDF) 71 Page - Texas Instruments