TPS25751D datasheet(42/89 Pages) TI1

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The TPS25751 has one I2C controller interface port. I2C is comprised of the I2C_SDA and I2C_SCL pins. This

interface can be used to read from or write to external target devices.

During boot, the TPS25751 attempts to read patch and Application Configuration data from an external

EEPROM with a 7-bit target address of 0x50. The EEPROM must be at least 32 kilo-bytes.

Table 8-4. I2C Summary

I2C BUS

TYPE

TYPICAL USAGE

I2Ct

Target

Optionally can be connected to an external MCU. Also used to load the patch and application

configuration.

I2Cc

Controller

Connect to a I2C EEPROM, Battery Charger. Use the LDO_3V3 pin as the pullup voltage. Multi-

controller configuration is not supported.

8.3.11.1 I2C Interface Description

The TPS25751 supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the serial

clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data

transfer can be initiated only when the bus is not busy.

A controller sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input

is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit

(MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred

during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period

as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends

a Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a

target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must

generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to

ensure proper operation.

A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the target. The controller receiver holding the SDA line high does this.

In this event, the transmitter must release the data line to enable the controller to generate a Stop condition.

Figure 8-27 shows the start and stop conditions of the transfer. Figure 8-28 shows the SDA and SCL signals for

transferring a bit. Figure 8-29 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

Start Condition

Stop Condition

SDA

SCL

Figure 8-27. I2C Definition of Start and Stop Conditions

TPS25751

SLVSH93 – OCTOBER 2023

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