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TPS25751D Datasheet(PDF) 61 Page - Texas Instruments |
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TPS25751D Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 89 page  Table 9-4. Minimum Trace Width (continued) Route Minimum Width (mils) GPIO 4 9.4.1.2 Layout Example 9.4.1.2.1 TPS25751D Schematic Layout Example Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the TPS25751D. LDO_3V3 1 VIN_3V3 38 ADCIN1 2 ADCIN2 3 GPIO0 5 GPIO1 6 GPIO2 7 GPIO3 19 GPIO4/USB_P/MD1 26 GPIO5/USB_N/MD2 27 GPIO6 37 GPIO7 36 GPIO11 13 I2Ct_SCL 9 I2Ct_SDA 8 DRAIN 15 DRAIN 30 DRAIN_PAD 40 I2Cc_IRQ 18 I2Ct_IRQ 10 LDO_1V5 4 PP5V 34 PPHV 20 I2Cc_SCL 17 I2Cc_SDA 16 VBUS 32 VBUS_IN 23 CC1 28 CC2 29 GND 11 GND 12 GND 14 GND 31 GND_PAD 39 VBUS 33 VBUS_IN 24 VBUS_IN 25 PP5V 35 PPHV 21 PPHV 22 TP S 25751DREFR U1 GND A1 S S TXp1 A2 S S TXn1 A3 VBUS A4 CC1 A5 Dp1 A6 Dn1 A7 SBU1 A8 VBUS A9 SSRXn2 A10 SSRXp2 A11 GND B12 SSRXp1 B11 SSRXn1 B10 VBUS B9 SBU2 B8 CC2 B5 VBUS B4 S S TXn2 B3 S S TXp2 B2 GND B1 GND A12 SHIELD S1 SHIELD S2 SHIELD S3 SHIELD S4 Dp2 B6 Dn2 B7 J1 DX07S 024J J 2R1300 P 3V3 VBUS PP5V LDO_3V3 LDO_1V5 0.01uF C2 0.01uF C3 0.01uF C4 0.01uF C5 GND 10uF C9 GND 100uF C6 100uF C7 I2Ct_SCL I2Ct_SDA I2Ct_IRQ I2Cc_SCL I2Cc_SDA I2Cc_IRQ R6 10kΩ R3 10kΩ LDO_3V3 R5 2.2kΩ R4 2.2kΩ R2 2.2kΩ R1 2.2kΩ GND GP IO0 GP IO1 GP IO2 GP IO3 GP IO4 GP IO5 GP IO6 GP IO7 GP IO11 DRAIN ADCIN1 ADCIN2 330pF C11 330pF C10 GND CC1 CC2 22uF C12 22uF C13 GND PPHV P3V3 LDO_1V5 LDO_3V3 GND GND GND GND GND VBUS VBUS VBUS VBUS CC1 CC2 4.7uF C1 10uF C17 10uF C16 10uF C15 10uF C8 0.1uF C14 TVS 2200DRVR U2 GND Figure 9-26. TPS25751D Example Schematic 9.4.1.2.2 TPS25751D Layout Example - PCB Plots The following TPS25751D PCB Layout figures show the recommended layout, placement, and routing. www.ti.com TPS25751 SLVSH93 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TPS25751 |
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