PM3350-SW datasheet(189/224 Pages) PMC

189 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

187

with D0 representing the data read from ByteReadAddress and D4 the data be read

from "ByteReadAddress+4" the Switch Processor firmware must do the following:

•

write RPCIMADDRh/l register to "ByteReadAddress"

•

write the RPCICMD register:

BYTECOUNT=8'h5, cmd[1:0]=memory_read_cmd

•

the read transaction will then occur on the PCI bus. After the transaction has

completed and all 5 data bytes are in the RPCIM data FIFO, the rpcim_done

interrupt is asserted.

• during the firmware service routine the Switch Processor will read the

RPCIDATA register:

• 1st read from RPCIDATA returns first two data bytes: {D0,D1}

• 2nd read from RPCIDATA returns next two data bytes: {D2,D3}

• 3rd read from RPCIDATA returns the last data byte: {D4,8'hX}

RPCIM: zero-length transactions

If the Switch Processor firmware tries to initiate an RPCIM transaction having a

BYTECOUNT of size `0' then the RPCIM internal state machine will not leave state

IDLE.

RPCIM: writing to RPCICMD.BYTECOUNT field if the RPCIM is not IDLE

If the `rpcim_idle' coprocessor test condition line returns 0 (indicating that the RPCIM

module has a transaction in progress) then the BYTECOUNT field of the RPCICMD

results (i.e. PCI bus master error).

RPCIM: internal arbitration to PCI_BIU shared hardware resources

Since the RPCIM must share the PCI_BIU master write and read hardware with other

PCI (i.e. DMA) write and read channels on the PM3351 there must be some way to

determine which consumer is getting access to the interface. This is accomplished

using a simple request-grant protocol.

On the PM3351 the request/grant protocol betweent the RPCIM logic and the various

other DMA channels is done completely in hardware and is transparent to the

programmer.

PM3350-SW Datasheet(PDF) 189 Page - PMC-Sierra, Inc