PM3350-SW datasheet(185/224 Pages) PMC

185 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

183

• the value of the selected counter can be read from the CTRDATA

The Switch Processor can WRITE a selected Request or Acknowledge

counter as follows:

• the CTRSEL register is written with the CTRSEL.en_wr_counter bit

set (1) and the CTRSEL[3:0] field set to access the desired counter.

• the Switch Processor uses the MOVE or LDI assembly instructions to

write the desired value to the CTRDATA register.

• on the cycle after CTRDATA is written by the Switch Processor the

write data updates the selected Request/Acknowledge counter.

RPCIM Functional Block (PCI access DMA channel)

The purpose of the RPCIM logic block on the PM3351 is to allow the Switch Processor

to directly initiate PCI bus master transactions:

•

memory read transactions

•

memory write transactions

•

configuration read transactions

•

configuration write transactions

In normal Ethernet switching applications firmware will only utilize the RPCIM logic

during system initialization; it is the various dedicated DMA channels on the PM3351

that are used to initiate all of the PCI master transactions on the PCI expansion bus that

are required by the ELAN switch protocol. During system initialization all of the PCI bus

transactions that the Master chip in a system does to initialize Slave chips is done

utilizing the RPCIM logic block.

Outline of RPCIM memory/configuration WRITE transactions:

For write transfers, the data to be written to the PCI bus must be broken up into a

sequence of transactions that are from 1 to 63 bytes in size. The data to be written to

the PCI bus is held in an internal RPCIM data FIFO which is accessible via writes to

the RPCIDATA register. The data FIFO write pointer is auto-incremented on each write

to the RPCIDATA register. The transfer is initiated by writing to a series of Switch

Processor accessible control registers: RPCIADDR (address) and RPCICMD

(command related). The write to the RPCICMD register signals the RPCIM internal

state machine to start the PCI master write transaction.

PM3350-SW Datasheet(PDF) 185 Page - PMC-Sierra, Inc

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