PM3350-SW datasheet(187/224 Pages) PMC

187 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

185

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whether the entire block transfer will occur on the PCI bus as a single PCI bus

transaction (which may result in greater latency of other internal PCI master

read consumers to complete a PCI read transaction). The maximum number of

bytes that can be read in a single transaction by the PM3351 is 255.

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or as a series of 1-64 bytes transactions.

The PCI read transaction will occur on the PCI bus as one burst read transaction.

The PCI read transfer is initiated by writing the RPCIADDR and RPCICMD registers.

The write to the RPCICMD register signals the RPCIM internal state machine to start

the PCI master read or configuration read transaction. The RPCIM must arbitrate with

the other internal DMA channels that can initiate PCI read transactions for access to a

shared hardware resource: the Master Read Command (MCF) and Master Read Data

(MRF) FIFOs that are part of the internal PCI bus interface logic (PCI_BIU). The arbiter

for access to the MCF/MRF FIFOs is internal to the RPCIM logic. The grant for the

read interface, `rrd_gt', is set on the cycle before the RPCIM logic writes the MCF CMD

word to the MCF FIFO.

When the desired read transaction is occuring on the PCI bus the read data is written

into the internal RPCIM data FIFO until the first of these occur:

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64 bytes of data have been read from the MRF FIFO

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or the internal BYTECOUNT size field has decremented to 0 indicating that all

data has been read.

The rpcim_done line is asserted indicating that the Switch Processor can burst read the

RPCIMDATA register to access the read data. Coincident with assertion of rpcim_done,

if the next_BYTECOUNT field has decremented to `0' then the internal arbiter bit

"rrd_gt" is deasserted (this will always be true if RPCIM.BYTECOUNT is never written to

greater than 64). next_BYTECOUNT is an internal counter that is preloaded with

BYTECOUNT and decrements as data is read.

The Switch Processor takes the rpcim_done interrupt:

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Switch Processor reads the read data from the RPCIMDATA control register.

Every read returns either one or two valid data bytes and increments the internal

RPCIM data register address and decrements next_BYTECOUNT.

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after the Switch Processor has read all of the data that it wants to read out of

the RPCIM data FIFO it pulses the `clr_rpcim_done' line.

Upon assertion of the `clr_rpcim_done' line the rpcim_done line is deasserted and

next_BYTECOUNT is assigned to RPCIM.BYTECOUNT. If RPCIM.BYTECOUNT is `0'

PM3350-SW Datasheet(PDF) 187 Page - PMC-Sierra, Inc

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