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PM3350-SW Datasheet(PDF) 184 Page - PMC-Sierra, Inc |
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PM3350-SW Datasheet(HTML) 184 Page - PMC-Sierra, Inc |
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184 / 224 page ![]() ELAN 8X10 PM3350 ELAN 8 X10 DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY 182 CTRSEL[3:0]: Selects the counter to view . CTRSEL[3:0] CTRDATA[11:0] 0000 rcountq0 0001 rcountq1 0010 rcountq2 0011 rcountq3 0100 rcountq4 0101 rcountq5 0110 rcountq6 0111 rcountq7 1000 acountq0 1001 acountq1 1010 acountq2 1011 acountq3 1100 acountq4 1101 acountq5 1110 acountq6 1111 acountq7 Register 0x2F: Request/ack counter data reg (cr15) Bit Type Function Default Bit 15 to 0 R/W CTRDATA[15:0] 0 During normal switching applications the CTRDATA register will be left in the default state and is unused. It is implemented solely for factory test. CTRDATA[15:0]: The data from the selected counter bank. This allows the Switch Processor to read or write one of the eight RCOUNT or eight ACOUNT registers that are also mapped into the PCI host register space. The Switch Processor can READ a selected Request or Acknowledge counter as follows: • the CTRSEL register is written with the CTRSEL.en_wr_counter bit clear (0) and the CTRSEL[3:0] field set to access the desired counter. • there is a minimum of one processor delay slot |
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