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PM3350-SW Datasheet(PDF) 186 Page - PMC-Sierra, Inc

Part # PM3350-SW
Description  8 PORT ETHERNET SWITCH
PDF  224 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM3350-SW Datasheet(HTML) 186 Page - PMC-Sierra, Inc

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ELAN 8X10
PM3350 ELAN 8 X10
DATA SHEET
PMC-970109
ISSUE 3
8 PORT ETHERNET SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
184
The RPCIM must arbitrate with the other internal DMA channels that can initiate PCI
write transactions for access to a shared hardware resource: the PCI Master Write
FIFO (MWF FIFO) that is part of the internal PCI Bus Interace Unit (PCI_BIU). The
arbiter for access to the MWF FIFO is internal to the RPCIM logic. The grant for the
write interface, `rwr_gt', is set on the cycle before the RPCIM writes the command word
in the MWF FIFO.
Upon writing the last word of the command/address/data into the MWF FIFO for a given
transaction, the following occurs concurrently:
•
the rpcim_done line is asserted (this maps to one of the interrupt lines on the
PM3351 Switch Processor).
•
rwr_gt is deasserted; this allows another DMA channel to perform PCI write
transactions.
On the PCI bus the write transaction will appear as a single burst transaction of
"BYTECOUNT" bits.
The Switch Processor takes the rpcim_done interrupt:
•
Switch Processor does a clr_rpcim_done flip at beginning of the interrupt
routine, which deasserts the rpcim_done interrupt and clears state of the RPCIM
module (returns the internal state machine to IDLE and resets data FIFO write
and read pointers).
•
if (the Switch Processor wants to continue the DMA transfer) the Switch
Processor firmware computes the next PCI address and writes the new
ByteWriteAddress into RPCIADDR:
• ByteWriteAddress = ByteWriteAddress + sizeof_last_BYTECOUNT
(which is probably 64);
•
Switch Processor firmware writes data for the next transfer to the RPCIDATA
register
•
Switch Processor writes the RPCIMD register with BYTECOUNT of new
transaction.
Outline of RPCIM memory/configuration READ transactions:
Although there is only one hardware mode of operation for performing read transactions
the Switch Processor firmware can determine how transactions of larger than 64 bytes
are handled:



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