PM3350-SW datasheet(183/224 Pages) PMC

183 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

181

packet buffer. These registers are modified by either writes by the RISC or

by the DMA upon transfer of the packet buffer.

Bit

Type

Function

Default

Bit 15

R/W

CTRSELTM

Bit 14

R/W

EN_WR_COUNTER

Bit 13

R/W

DISABLE_REQ_INT

Bit 12

R/W

DISABLE_ACK_INT

Bit 11 to 4

Unused

Bit 3 to 0

R/W

CTRSEL[3:0]

During normal switching applications the CTRLSEL register will be left in the

default state and is unused. It is implemented solely for factory test.

CTRSELTM:

The testmode bit for counter bank testing. This bit must be a logic 0.

EN_WR_COUNTER:

When set to a logic 1, this bit allows req/ack counters to be written by the

Switch Processor.

DISABLE_REQ_INT:

When set to a logic 1, this bit disables the generation of the REQ_INT

interrupt line.

DISABLE_ACK_INT:

When set to a logic 1, this bit disables the generation of the ACK_INT

interrupt line.

PM3350-SW Datasheet(PDF) 183 Page - PMC-Sierra, Inc

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