PM3350-SW datasheet(136/224 Pages) PMC

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ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

134

variable is decremented by 1; if the result is equal to or less than zero, the broadcast or

multicast frame is discarded, as the broadcast frame limit has been exceeded. If the

result is greater than zero, the broadcast/multicast frame is accepted for processing in

the usual manner (i.e., queued to the target transmit ports), and the MaxBcstFrames

variable is updated accordingly. Whenever a broadcast or multicast frame has been

completely transmitted or transferred (i.e., the packet buffer chain holding the broadcast

or multicast frame has been returned to the free packet buffer pool), the

MaxBcstFrames variable is incremented, allowing additional broadcast or multicast

frames to be accepted. Note that the broadcast/multicast frame limit is applicable to

frames received over the PCI expansion port, as well as frames received over local

MAC ports.

The MaxBcstFrames variable is maintained by the Switch Processor firmware in cached

data space, and is hence not accessible directly over the PCI bus interface. The

messaging interface must be used to update it. This operation is TBD.

Transmit Queue Management

The ELAN 8x10 implements two mechanisms to monitor and manage the transmit

queues (i.e., the queues holding frames waiting to be transmitted out the local MAC

ports) in the system.

Transmit Queue Purging

The first mechanism is intended to ensure that frames do not persist in the transmit

queues for too long before being transmitted. This can happen if the medium

associated with a MAC channel is continually busy due to a malfunctioning system or a

jabbering upstream host or switch, or if some hardware fault is present that prevents

frames from being transmitted. In this case, it is possible that the transmit queue

belonging to the MAC channel will fill up with frames that will never be sent out, and

thus their packet buffers will never be released back to the free pool. In extreme cases,

the entire buffering in the system can ultimately be consumed by these blocked frames,

bringing the system to a halt.

To detect such a condition, the ELAN 8x10 employs a mark-and-sweep algorithm on

the entries in the various transmit queues, using the lower 4 bits (i.e., the TypeSpecific

subfield) of the 8-bit Flags fields of the data descriptors placed on the transmit queues

to hold a marker. This field is initially set to zero by the switching firmware when frames

are queued to the transmit queues, and the data descriptors pointing to the frame data

are linked into the linked-lists forming the queues. The ELAN 8x10 Switch Processor

then executes a background task that runs periodically at a pre-set interval (normally

200 milliseconds). This background task sweeps over all of the transmit queues in the

device, inspecting the data descriptors (if any) at the heads of the queues. For each

data descriptor, the background task checks the Flags field of the descriptor, as follows:

PM3350-SW Datasheet(PDF) 136 Page - PMC-Sierra, Inc

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