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PM7375-SC Datasheet(PDF) 151 Page - PMC-Sierra, Inc |
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PM7375-SC Datasheet(HTML) 151 Page - PMC-Sierra, Inc |
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151 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 135 10.1.26 Register 0x31 (0x0C4): RPOP Interrupt Status Bit Type Function Default Bit 15 Unused X Bit 14 Unused X Bit 13 Unused X Bit 12 Unused X Bit 11 Unused X Bit 10 Unused X Bit 9 Unused X Bit 8 Unused X Bit 7 R PSLI X Bit 6 Unused X Bit 5 R LOPI X Bit 4 Unused X Bit 3 R PAISI X Bit 2 R PRDII X Bit 1 R BIPEI X Bit 0 R FEBEI X This register allows identification and acknowledgment of path level alarm and error event interrupts. These bits (and the interrupt) are cleared when this register is read. FEBEI, BIPEI: The BIPEI and FEBEI bits are set to logic one when the corresponding event, a path BIP-8 error or path FEBE is detected. PRDII, PAISI, LOPI: The PRDII, PAISI, and LOPI bits are set to logic one when a transition occurs in the corresponding alarm state. PSLI: The PSLI bit is set to logic one when a change is detected in the path signal label register. The current path signal label can be read from the RPOP Path Signal Label register. |
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