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XIO2000A Datasheet(PDF) 135 Page - Texas Instruments

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Part # XIO2000A
Description  PCI Express to PCI Bus Translation Bridge
PDF  155 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

XIO2000A Datasheet(HTML) 135 Page - Texas Instruments

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Memory-Mapped TI Proprietary Register Space
125
April 2007
SCPS155B
6.23 Serial IRQ Mode Control Register
This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode
control register in the classic PCI configuration space (offset E0h, see Section 4.72). See Table 6−12 for a
complete description of the register contents.
Device control memory window register offset:
48h
Register type:
Read-only, Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
Table 6−12. Serial IRQ Mode Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:4
RSVD
R
Reserved. Returns 0h when read.
3:2†
START_WIDTH
RW
Start frame pulse width. Used to set the width of the start frame for a SERIRQ stream.
00 = 4 clocks (default)
01 = 6 clocks
10 = 8 clocks
11 = Reserved
1†
POLLMODE
RW
Poll mode. This bit selects between continuous and quiet mode.
0 = Continuous mode (default)
1 = Quiet mode
0†
DRIVEMODE
RW
Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.
0 = Drive high (default)
1 = Tri-state
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.



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