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TMPR3911 Datasheet(PDF) 122 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 122 Page - Toshiba Semiconductor |
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122 / 462 page ![]() Chapter 4 BIU Module 4-22 Figure 4.3.7 I/O Access to Card The PCMCIA specification provides for a WAIT* signal that allows the Card to halt the bus cycle until the WAIT* signal is de-asserted. This allows the Card to control the access time. The WAIT* signal will assert at the beginning of the cycle and the cycle should not terminate until the WAIT* signal becomes de-asserted. There are separate WAIT* signals provided for each Card: WAIT2* and WAIT1*. The WAIT* signals are sampled on two consecutive rising edges of CLK. If the WAIT* signal is low, the access time counter will freeze until the WAIT* signal goes high. This function will only occur if the WAIT function is enabled using the CARDxWAITEN control bit. If the WAIT function is not enabled, the WAIT* signal is ignored. Figure 4.3.6 shows the timing for Card WAIT accesses. Figure 4.3.8 Card Wait Timing DCLKOUT ALE A[12:0] D[31:16] CARDxCSH*/L* RD* 4 ×CARDxIOACCVAL–4 4 ×CARDxIOACCVAL–4 WE* CARDDIR* CARDDREG IORD* IOWR* DCLKOUT ALE A[12:0] D[31:16] CARDxCS* RD* WAITx* |
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