TMPR3911 datasheet(124/462 Pages) TOSHIBA

124 / 462 page

Chapter 4 BIU Module

4-24

4.4

DRAM and SDRAM Controller

The DRAM and SDRAM Controller generates the required control signals to interface to DRAM and

SDRAM devices. Two separate banks are supported and each bank can contain either DRAM or SDRAM,

with the only restriction being that Bank 1 cannot contain SDRAM if Bank 0 contains DRAM. The DRAM

and SDRAM Controller supports 4-Mbit, 16-Mbit and 64-Mbit devices in various bus configurations. In

order to maximize the memory bandwidth, both the DRAM and SDRAM devices can be kept in page mode

to complete burst read cycles and in-page write cycles.

4.4.1

Memory Chips Supported

Table 4.4.1 shows the different DRAM and SDRAM chips that are supported by the DRAM and

SDRAM Controller. Also shown is the Row and Column configuration for the supported chips.

SDRAM chips also contain two banks that are selectable through the address space.

Table 4.4.1 Supported DRAM and SDRAM Chips

Number of

Bank

Row

Address

Column

Address

Memory Size

Memory Type

–

256 K

× 16

4-Mbit DRAM

–

256 K

× 16

4-Mbit DRAM

–

512 K

× 84-Mbit DRAM

–10

1 M

× 16

16-Mbit DRAM

–11

1 M

× 16

16-Mbit DRAM

–12

1 M

× 16

16-Mbit DRAM

–11

2 M

× 8

16-Mbit DRAM

–12

2 M

× 8

16-Mbit DRAM

211

2 M

× 8

16-Mbit SDRAM

211

1 M

× 16

16-Mbit SDRAM

–11

4 M

× 16

64-Mbit DRAM

–12

4 M

× 16

64-Mbit DRAM

–12

8 M

× 8

64-Mbit DRAM

212

8 M

× 8

64-Mbit SDRAM

212

4 M

× 16

64-Mbit SDRAM

213

8 M

× 8

64-Mbit SDRAM

412

4 M

× 16

64-Mbit SDRAM

412

8 M

× 16

128-Mbit SDRAM

Four-bank SDRAM

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