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TMPR3911 Datasheet(PDF) 128 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 128 Page - Toshiba Semiconductor

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Chapter 4 BIU Module
4-28
ENBANKxOPT = 1
ENBANKxHDRAM = 0
Figure 4.4.4 Write with ENBANKOPT Set followed by Refresh Cycle (DRAM)
(2) DRAM Initialization
When the DRAM is first powered up there are several things that must be done before accessing the
DRAM. First the Memory Configuration Registers must be properly configured for the chosen DRAM
and bus configuration. Next, after a delay of at least 100
µs after the power is asserted to the DRAM,
the refresh should be enabled. The DRAM should not be accessed until at least eight CAS* before
RAS* refresh cycles occur. After this procedure is completed the DRAM can be accessed.
DCLKOUT
A[12:0]
D[31:0]
RAS*
CAS*
WE*
ROW
COL



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