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TMPR3911 Datasheet(PDF) 131 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 131 Page - Toshiba Semiconductor |
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131 / 462 page ![]() Chapter 4 BIU Module 4-31 Figure 4.4.6 Word Read and Write to 16-Bit SDRAM Figure 4.4.7 4-Word Burst Read and Byte Write to 16-Bit SDRAM (6) Support of Four-Bank SDRAM (only by TMPR3911BU/BXB and TMPR3912XB-92/AU-92) The TMPR3912XB-92/AU-92 supports four-bank SDRAM. When DRAM banks 0 and 1 are 16-bit SDRAM, Addr[21] is output from the CAS2* pin. Also, by setting ROW and COL as follows, Addr[22] can be output from the A[12] pin. ROW: 22, 18, 20, 19, 17:9 (ROWSEL = 01) COL: 22, X, φ, X, X, 8:1 (COLSEL = 1000) The CAS2* pin (Addr[21]) and A[12] pin (Addr[22]) can be connected to the four-bank SDRAM bank select pin so that the CAS2* and A[12] pins are used for the bank select signal. DCLKOUT A[12:0] D[7:0] DCS0/1* RAS* CAS* WE* ROW ROW COLUMN COLUMN 32-bit 32-bit WRITE DQMH DQML DCKE DCLKOUT A[12:0] D[7:0] DCS0/1* RAS* CAS* WE* ROW COL COLUMN 4 WORD BURST READ BYTE WRITE DQMH DQML DCKE COL COL ROW COLUMN |
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