TMPR3911 datasheet(133/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-33

4.5.3

Watch Dog Timer

The Watch Dog Timer prevents accesses to reserved memory locations from hanging the BIU. The

Watch Dog Timer consists of a 10-bit down-counter whose initial value is determined by the

WATCHTIMEVAL[3:0]

control

bits

the

Memory

Configuration

The

WATCHTIMEVAL[3:0] control bits are loaded into the upper 4 bits of the 10-bit counter and the lower

6 bits are loaded with $3F. The counter uses the CLK signal to count. The Watch Dog Timer rate is

determined by the following equation:

Watch Dog Timer Rate

(

CLK

VAL[3

(WATCHTIME

*1fCLK is the frequency of the CLK signal and is ×4 the frequency of SYSCLK (that is,

when SYSCLK is 9.216 MHz, fCLK is 36.864 MHz (*2); when SYSCLK is 11.520

MHz, fCLK is 46.08 MHz.

Note that these valve is the case that the RF function is not used. Therefore, In

case of TMPR3911, fCLK is a half of this valve, which means 18.432 MHz

The Watch Dog Timer is enabled using the ENWATCH control bit in the Memory Configuration 4

begin a memory transaction. If the Watch Dog Timer reaches a count of zero before the Memory State

Machine asserts the Ack signal, the BusError signal is asserted to end the memory transaction. There

are two possible ways that this can occur. First, if the address provided by the CPU interface to the

Address Decoder is pointing to any of the reserved locations or to any of the chip selects that are not

enabled, then the Memory State Machine will not respond with an Ack. Secondly, if the WAIT function

is enabled to Card 2 or Card 1, then the WAIT2* or WAIT1* signals must de-assert before the Watch

Dog Timer reaches a count of zero, otherwise the BusError signal will be asserted and the Card access

will be aborted.

4.5.4

Memory Power Down

The memory interface is powered down whenever the MEMPOWERDOWN control bit is set in the

Memory Configuration 4 Register. When this bit is set, the Halt signal will be asserted to the CPU

Interface, the DRAM and/or SDRAM will be placed into self refresh mode, and all memory interface

signals will be driven low. The memory interface will wake up whenever the CPU Interface asserts the

HaltCycle signal and the address defined by the Addr[31:2] bits correspond to an address other than

internal function registers. When the memory interface wakes up, the DRAM and/or SDRAM are taken

out of self refresh mode and the Halt signal is de-asserted to allow the CPU Interface to launch memory

transactions. Figure 4.5.1 and Figure 4.5.2 show timing for the wake-up and power-down of the

memory interface.

TMPR3911 Datasheet(PDF) 133 Page - Toshiba Semiconductor

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