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TMPR3911 Datasheet(PDF) 134 Page - Toshiba Semiconductor

Part # TMPR3911
Description  32-Bit TX System RISC TX39 Family
PDF  462 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 134 Page - Toshiba Semiconductor

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Chapter 4 BIU Module
4-34
Figure 4.5.1 Memory Interface Wake-Up
Figure 4.5.2 Memory Interface Power Down
When the memory interface is powered down all memory signals are driven low. The order in which
they are driven low is important because DRAM devices enter self refresh mode by asserting CAS*
before RAS*, and SDRAM devices enter self refresh mode by de-asserting DCKE while DCS0* and/or
RAS1*, RAS0* and CAS0* are asserted with WE* not asserted. Once the SDRAM enters self refresh
mode, DCLKOUT can be turned off. The ordering makes it possible to put both DRAM and SDRAM
devices into self refresh mode with only one time setting required. When the memory interface comes
out of self refresh mode, all signals are de-asserted. DCKE must de-assert one clock later in order to
properly bring the SDRAM out of self refresh mode. After exiting self refresh mode, the Halt signal
will not be released for several clocks to allow the DRAM and SDRAM to finish exiting self refresh
mode.
DCLKOUT
A[12:0]
D[31:0]
DCS0*
RAS1*
RAS0*
CAS3-0*
WE*
DQMH/L
DCKE
DCLKOUT
A[12:0]
D[31:0]
DCS0*
RAS1*
RAS0*
CAS3-0*
WE*
DQMH/L
DCKE



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