TMPR3911 datasheet(130/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-30

(4) SDRAM Power Down Mode

The DCKE signal is provided for putting the SDRAM into Power Down Mode. The Power Down

Mode feature can be enabled or disabled using the ENSDRAMPD control bit in the Memory

Configuration 0 Register. When this bit is set, the DCKE signal will be held low whenever there are no

accesses to the SDRAM device for 7 CLK periods. Once a read, write or refresh is initiated to the

SDRAM, the DCKE signal is asserted to bring the device out of Power Down Mode. Power Down

Mode helps to reduce power dissipation in the SDRAM device when there are no accesses. During

Memory Power Down the SDRAM device is placed into self refresh mode for maximum power savings

and the DCLKOUT signal.

(5) SDRAM Timing

Figure 4.4.5 through Figure 4.4.7 show a few examples of the SDRAM timing. The first chip select

(assertion of CS*) is used to latch the ROW address. Subsequent chip selects will either read or write

data, and the final chip select is used to precharge the bank. Note from Table 4.4.2 that address bit 10

for 16-Mbit parts and address bit 11 for 64-Mbit parts is always a zero during the column address. This

is done to ensure that auto precharge is never latched during a read or write command and also will

cause only the bank that is being accessed to be precharged during the precharge command. Since the

burst size of the SDRAMs is always setup to 32 bits, reads will always be 32 bits without regard to the

actual number of bytes requested by the CPU. Writes are also 32 bits, but the data mask signals DQMH

and DQML will mask out the bytes that should not be written, thus allowing for Triple Byte, Half-Word

and Byte writes.

Figure 4.4.5 Word Read and Write to 8-bit SDRAM

DCLKOUT

A[12:0]

D[7:0]

DCS0/1*

RAS*

CAS*

WE*

ROW

COLUMN

32-bit

READ

32-bit

WRITE

DQMH

DQML

DCKE

TMPR3911 Datasheet(PDF) 130 Page - Toshiba Semiconductor