TMPR3911 datasheet(129/462 Pages) TOSHIBA

129 / 462 page

Chapter 4 BIU Module

4-29

4.4.4

SDRAM

(1) SDRAM

SDRAM devices are supported in Bank 1 and Bank 0. Each Bank can independently be configured to

support either 16-bit or 8-bit SDRAMs. Bank 1 uses RAS1* as the chip select for the SDRAM and

Bank 0 uses DCS0*. All other control signals are shared between the two banks.

The clock for the SDRAM devices is the DCLKOUT signal which nominally runs at the clock twice

the rate of the CLK signal. Reads from the SDRAMs occur on every DCLKOUT cycle, such that the

reading of all 32 bits for 16-bit SDRAMs can happen within a single CLK cycle. A 16-bit SDRAM

configuration provides the maximum memory bandwidth and once a read cycle begins, the CPU will

not stall since 32 bits are read on each cycle. All 8-bit SDRAMs require 2 CLK cycles to read 32 bits of

data. During a burst read the SDRAM devices are kept in page mode for the entire read cycle.

The SDRAM devices are also kept in page mode during in-page write cycles. All 16-bit SDRAMs

can keep up at 32 bits per CLK cycle, which can provide a long write block without stalling the CPU.

All 8-bit SDRAMs require twice the number of cycles. Tri, Half-Word and Byte writes are supported to

the SDRAM devices using the DQMH and DQML signals. These signals provide a data mask so that

only the desired bytes will be written. DQMH is used for the upper 8 bits in a 16-bit SDRAM

configuration and DQML is used for the lower 8 bits. For 8-bit SDRAMs only DQML is used. The data

mask signals DQMH and DQML are required because the SDRAM is setup to always read or write 32

bits of data at a time. The data mask signals will “mask out” the bytes that should not be written during

partial Word stores.

(2) SDRAM Initialization

Prior to accessing an SDRAM device, an initialization procedure must be followed. First, all Memory

Configuration Registers must be properly initialized for the chosen SDRAM and bus configuration.

Next, after a pause of at least 200

µs after power is applied to the SDRAM, a command must be sent to

precharge the SDRAM banks. The command is sent by writing to the SDRAM Bank 1 and/or Bank 0

Mode Register address with Data[31] set high when the TMPR3911/12 is mapped as big endian, or with

Data[7] set high when the TMPR3911/12 is mapped as little endian. Setting this bit will cause a

Precharge All command to be sent to the SDRAM instead of writing to the Mode Register. Next, the

Mode Register must be properly initialized. Finally, refresh should be enabled and at least 8 refresh

cycles must occur prior to reading or writing from or to the SDRAM.

(3) SDRAM Mode Register

An SDRAM contains a write-only Mode Register that defines the parameters for accessing the

device. The mode register must be initialized prior to reading or writing from the SDRAM. They can be

written via the SDRAM Bank 1 and SDRAM Bank 0 addresses as shown in the System Address Map.

When writing to the mode register, the data from the CPU Interface on Data[12:0] (Data[20:16, 31:24])

is placed on A[12:0], and Data[31] (Data[7]) must be a zero when the TMPR3911/12 is mapped as big

endian (little endian). This is done because the Mode Register receives its data on the address bus

instead of the data bus. The SDRAM should be configured for the following settings: Burst Length

= 4

(for 8-bit SDRAM) or Burst Length

= 2 (for 16-bit SDRAM), CAS Latency = 3, Burst Type =

Sequential, Write Mode = Burst Write.

TMPR3911 Datasheet(PDF) 129 Page - Toshiba Semiconductor

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