TMPR3911 datasheet(132/462 Pages) TOSHIBA

132 / 462 page

Chapter 4 BIU Module

4-32

4.5

Arbitration

The Arbitration logic contains the Refresh Controller for Bank 1 and Bank 0, support for External Bus

Master, the Watch Dog Timer for terminating hung memory accesses, and Memory Power Down logic for

placing the SDRAM and/or DRAM into self refresh mode.

4.5.1

Refresh Controller

The Refresh Controller logic contains separate refresh counters for Bank 1 and Bank 0. Each counter

is a 6-bit counter that uses the 32 kHz clock for the counter. The refresh rate is set using the

RFSHVAL1[5:0] and RFSHVAL0[5:0] control bits in the Memory Configuration 4 Register. These

values are loaded into the respective refresh counter. The refresh counter will down count and when it

reaches a count of zero, refresh will be inserted. If the RFSHVALx control bits are set to $00, the

counter is not used and instead refresh is generated based on both the rising and falling edge of the 32

kHz clock. This is required to generate a 15.26

µs refresh rate required by some DRAMs or SDRAMs.

RFSHVALx control bits set to $01 will cause a refresh rate of 61.04

µs and additional values will

increase the refresh rate by increments of 30.52

µs. When it is time for the Refresh Controller to insert

refresh, the Halt signal will be asserted to the CPU Interface. Once the CPU Interface asserts the Halted

signal, the Refresh Controller will generate the appropriate control signals that will cause the DRAM &

SDRAM control logic to provide refresh for the memory devices. Once the Refresh Controller has

completed inserting refresh, the Halt signal will be de-asserted so that the CPU Interface can continue

running.

4.5.2

External Bus Master

The External Bus Master logic allows an external device to take control of the memory signals so that

memory can be shared with an external device. The external device will request the bus by asserting the

DREQ* signal. Once the DREQ* signal is asserted, the Halt signal will be asserted to the CPU Interface

logic. Once the CPU Interface logic asserts the Halted signal, the External Bus Master logic will then

assert the DGRNT* signal to inform the external device that it now controls the memory bus. At the

same time that DGRNT* is asserted, the following signals are tri-stated: D[31:0], A[12:0], ALE, RD*,

WE*, CAS3*-CAS0*, RAS1*, RAS0*, DCS0*, DCKE, DQMH, DQML and CS0*. DCLKOUT will be

tri-stated if the ENDCLKOUTTRI control bit is set in the Memory Configuration 0 Register. Otherwise,

DCLKOUT will continue to run. Once the external device de-asserts DREQ*, DGRNT* will be de-

asserted, the memory signals will be driven by the TMPR3911/12, and the Halt signal will be de-

asserted so the CPU Interface can begin launching memory transactions. The external device should not

attempt to take over the memory signals for a long period of time, otherwise TMPR3911/12 DMA

events and refresh will be interrupted. The External Bus Master logic will not respond with a DGRNT*

if the memory interface is powered down.

TMPR3911 Datasheet(PDF) 132 Page - Toshiba Semiconductor

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