TMPR3911 datasheet(183/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-9

7.3.2

Transmitter

For the CHI transmit direction, Buffer-A and Buffer-B transmit holding registers are written either

from the DMA circuit or directly from the CPU. Each of these 2 holding registers are 32-bits wide, and

CHI control logic determines which byte from which holding register gets loaded at a given time into

the 8-bit transmit shift register. In addition, the byte data loaded from the holding register to the shift

is that the CHI Module operates in a ping-pong fashion. Each frame of data is partitioned into 2 buffers

(A and B); for example, with 64 timeslots total, the data is partitioned into 32 timeslots per buffer. The

ping-pong operation allows one buffer to be updated (via the DMA or CPU) while the other buffer is

being loaded into the shift register a byte at a time, depending on which timeslots are active. The ping-

pong operation is transparent to the CPU or DMA interface, since the CHI Module automatically points

to the correct A or B buffer at a given time and the CPU or DMA always accesses the same 32-bit

holding register for all transactions.

The transmit TDM switch control register is used to select ANY 4 channels per buffer to be loaded

from the holding register to the shift register. For example, if the CHI Module is configured for 32

timeslots per buffer (64 total timeslots), any 4 channels per buffer (8 total) can be selected out of the 32

available channels. The CHIDOUT signal is tri-stated during any of the non-selected channels. Each of

the 8 selected channels also has an individual control bit for enabling/disabling the timeslot.

Figure 7.3.2 shows how the transmit TDM switch works, for example, with 16 total timeslots.

byte3

byte2

byte1

byte0

TX HOLDING REGISTER A

BIT31…………………….BIT0

byte3

byte2

byte1

byte0

TX HOLDING REGISTER B

BIT31…………………….BIT0

ch0

ch1

ch2

ch3

Hi-Z

ch9

Hi-Z

ch11

Hi-Z

ch13 ch14

Hi-Z

BIT0……………….BIT31

BIT 16…13

8…15

24…31 0…7

CHINCHAN[4:0]

TXMSBFIRST

CHI Pointer Enable

CHI Transmit Pointer A

CHI Transmit Pointer B

0x07

0xFFxx0000

0x03020100

0x05010306

CHIDOUT

CHIFS

Figure 7.3.2 Transmit TDM Switch Example

7.3.3

Receiver

For the CHI receive direction, Buffer-A and Buffer-B receive holding registers are read either by the

DMA circuit or directly by the CPU. Each of these 2 holding registers are 32 bits wide, and CHI control

logic determines which byte to which holding register gets loaded at a given time from the 8-bit receive

shift register. In addition, the byte data loaded from the shift register to the holding register can be

MSB-first or LSB-first. Similar to the transmit direction, the receive section also operates in a ping-

pong fashion, allowing one buffer to be read (via the DMA or CPU) while the other buffer is being

loaded from the shift register a byte at a time, depending on which timeslots are active.

The receive TDM switch control register (independent from the transmit TDM switch control

timeslot.

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