TMPR3911 datasheet(187/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-13

The DMA buffer size is programmable (up to a maximum of 16 Kbytes) and the receive and transmit

buffer start addresses are also programmable (anywhere over the full 32-bit address space). Because

there are separate start addresses, the receive and transmit buffers can be configured to either reside in

different memory spaces or share the same memory space. The latter setup allows for overlapping

buffers for loopback purposes or for optimum memory allocation, for which the DMA logic supports

two full-duplex loopback modes. For one mode, receive DMA requests are issued first, followed by

transmit DMA requests. This ordering allows a receive-to-transmit immediate loopback via the DMA

buffer. For the second mode, transmit DMA requests are issued first, followed by receive DMA

requests. Thus, received samples are written to the DMA buffer location immediately after transmit

samples were read from that same location (which then became immediately available). This ordering

allows a single circular DMA buffer to be used for both transmit and receive samples.

The DMA buffers can be configured in a circular buffer mode or a one-time buffer mode. For the

circular mode, the DMA address is continuously incremented (each time a DMA acknowledge is

received from the TMPR3911/12’s central DMA controller) and rolls over back to the start address after

the end-of-buffer is reached and will continue operating in a continuous and circular manner. For the

one-time mode, the DMA logic will stop executing whenever the end-of-buffer is reached.

Because the CHI Module reads and writes a byte at a time between the shift registers and the 32 bit

holding registers, the software must pack and unpack these bytes to and from the 32 bit words in

memory in order to multiplex and demultiplex each channel for processing. Table 7.3.1 shows the

format and organization of the CHI channels within memory for DMA mode. Consecutive byte samples

for a given channel reside in memory every 8th byte.

Note that the byte lanes are swapped between the little- and big-endian modes. In the little-endian

mode, bits 31:24 of a word on the DMA buffer correspond to the byte lane with the address offset ‘+3’

and therefore to the ‘byte0’ in the CHI TX/RX holding register. On the contrary, in the big-endian

mode, bits 31:24 of a word on the DMA buffer correspond to the byte lane with the address offset ‘+0’

and therefore to the ‘byte3’ in the CHI TX/RX holding register.

Table 7.3.1 CHI DMA Memory Organization

(relative)

memory address

+0x0

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 0

+0x4

buffB, byte3

buffB, byte2

buffB, byte1

buffB, byte0

sample 0

+0x8

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 1

+0xC

buffB, byte3

buffB, byte2

buffB, byte1

buffB, byte0

sample 1

+0x10

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 2

etc.

For a given channel, the minimum input-to-output latency for the CHI data path is (4 cycles)

× (62.5

µs) = 250 µs, assuming an 8 kHz frame rate. These required 4 cycles are as follows:

•

1 cycle to load receive shift register into receive holding register

•

1 cycle for DMA of receive holding register data into receive memory space

•

(insert here any application-specific time required for processing of received data and moving

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