TMPR3911 datasheet(191/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-17

CHITXFSPOL:

This bit selects between positive (active high) or negative (active low) polarity for the

transmitted CHIFS signal pulse, relevant whenever the CHI Module is configured as master mode.

Setting this bit to a logic “1” selects negative polarity for the CHIFS pulse. Clearing this bit to a

logic “0” selects positive polarity for the CHIFS pulse.

CHIRXEDGE:

This bit selects whether to use either the rising edge or falling edge of CHICLK to sample the

receive data CHIDIN. Setting this bit to a logic “1” selects rising edge. Clearing this bit to a logic

“0” selects falling edge. CHIDIN must be stable before and after the specified CHICLK edge.

CHITXEDGE:

This bit selects whether to use either the rising edge or falling edge of CHICLK to clock out the

transmit data CHIDOUT. Setting this bit to a logic “1” selects rising edge. Clearing this bit to a

logic “0” selects falling edge.

CHIFSEDGE:

This bit selects whether to use either the rising edge or falling edge of CHICLK to sample the

receive frame sync CHIFS. This bit must be properly set in CHI sync master mode, as well as in

CHI sync slave mode. Setting this bit to a logic “1” selects rising edge. Clearing this bit to a logic

“0” selects falling edge. CHIFS must be stable before and after the specified CHICLK edge; In

CHI sync master mode, CHIFSEDGE must be equal to inverted CHITXFSEDGE.

CHITXFSEDGE:

This bit selects whether to use either the rising edge or falling edge of CHICLK to clock out the

transmit frame sync CHIFS, relevant whenever the CHI Module is configured as master mode.

Setting this bit to a logic “1” selects rising edge. Clearing this bit to a logic “0” selects falling

edge.

CHICLK2XMODE:

This bit selects between 1x and 2x clock modes. Setting this bit to a logic “1” selects 2x clock

mode, which means that the CHICLK frequency equals twice the serial data bit rate. Clearing this

bit to a logic “0” selects 1x clock mode, which means that the CHICLK frequency equals the serial

data bit rate.

CHIRXEN:

This bit is used to enable/disable CHI receive processing in the direct CPU read/write mode,

where the CPU reads the received data through the CHI RX holding register. Setting this bit to a

logic “1” enables CHI receive processing. Clearing this bit to a logic “0” disables CHI receive

processing, causing all received data to not be processed by the CHI module. This bit has no effect

when RX DMA is enabled.

CHITXEN:

This bit is used to enable/disable CHI transmit processing in the direct CPU read/write mode,

where the CPU writes the data to be transmitted through the CHI TX holding register. Setting this

bit to a logic “1” enables CHI transmit processing. Clearing this bit to a logic “0” disables CHI

transmit processing, causing the CHI serial transmitted data to be tri-stated. This bit has no effect

when TX DMA is enabled.

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