TMPR3911 datasheet(188/462 Pages) TOSHIBA

188 / 462 page

Chapter 7 CHI Module

7-14

Half-buffer and end-of-buffer DMA address counter interrupts are available, allowing the CPU to

minimize overhead and utilize the DMA buffer in a ping-pong fashion. For transmit mode, the CPU can

use these interrupts to fill or write one half of the buffer while the other half is being emptied by the

DMA controller for transmitting out the CHI. Similarly, for receive mode, the CPU can use these

interrupts to empty or read one half of the buffer while the other half is being filled by the DMA

controller from received CHI input samples.

Also available is a direct CPU read/write mode for bypassing the DMA, allowing the CPU to read or

write the CHI data on a sample by sample basis, if so desired. Separate DMA enables for receive and

transmit allow DMA to be setup for receive only (transmit via CPU), transmit only (receive via CPU),

receive and transmit, or none (receive and transmit via CPU).

The DMA circuit also provides an interrupt each time the DMA buffer pointer is incremented, which

occurs whenever a new sample is read from and/or written to the DMA buffer. This interrupt may be

useful for triggering a read of the DMA pointer status value, which is the actual 12-bit DMA address

counter output. This value indicates exactly where the current address is pointing to in the overall DMA

buffer.

7.3.6

Related Interrupts

CHI0_5INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the halfway point.

CHI1_0INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the end-of-buffer point.

CHIDMACNTINT:

Issues an interrupt each time the CHI DMA buffer pointer is incremented, which occurs

whenever a new CHI sample is read from and/or written to the CHI DMA buffer.

CHIININTA:

Issues an interrupt whenever a valid CHI input sample is available from CHI RX Holding

CHIININTB:

Issues an interrupt whenever a valid CHI input sample is available from CHI RX Holding

CHIACTINT:

Issues an interrupt whenever CHICLK is active. This is used for CHI wakeup purposes.

CHIERRINT:

Issues an interrupt whenever a CHI error is received. This interrupt is triggered if CPU or DMA

reading of the CHI RX Holding Registers does not keep up with the hardware filling of the CHI

RX Holding Registers or if CPU or DMA writing of the CHI TX Holding Registers does not keep

up with the hardware emptying of the CHI TX Holding Registers.

TMPR3911 Datasheet(PDF) 188 Page - Toshiba Semiconductor