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TMPR3911 Datasheet(PDF) 186 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 186 Page - Toshiba Semiconductor |
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186 / 462 page ![]() Chapter 7 CHI Module 7-12 7.3.5 DMA Address Generation The CHI Module provides support for 2 full-duplex DMA channels: receive and transmit. The circuit used to generate the DMA address, as well as half-buffer and end-of-buffer interrupts is shown in Figure 7.3.4. 12 30 12 12 HALF-BUFFER INTERRUPT ONE-TIME VS. CIRCULAR MODE END-OF-BUFFER INTERRUPT DMA CONTROL FROM CPU DMA ADDR RX START ADDR DMA RD/WR mode CLK 30 TX START ADDR 2:1 DMA CNTL REG CNT LOAD LOGIC BUFFER SIZE CMP CMP ADDR CNT ÷ 2 Figure 7.3.4 CHI DMA Address Generation |
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